N4902B serialbert 7 gbps technical specification version 1.0
general the N4902B serialbert 7 gbps operates within a range from 620 mbps up to 7 gbps. a vailable conf igurations are: one pattern generator and one error detector one pattern generator only one error detector only key values & benefits range of operation 620 mbps to 7 gbps jitter injection, jitter tolerance measurement capabilities true differential data generation and anal ysis cdr with ranges at approximately 3 gbps and 6 gbps intuitive, state-of-t he-art windows xp. touchscreen user inter face inter-operability betw een N4902B and ot her instruments compatability with existing remote commands e.g. agilent 71612 and 86130a series signal integ rity fast est transition times pattern generator pattern generation for prbs or memory based patterns flexible lev els addressing a br oad range of technologies, e.g. ecl, pecl (3.3v), lvds, cml error detector ber measurements automatic threshold sampling p oint search data polarity g. 821 measurement measurement suite auto alignment measurement features output t iming jitter spectral jitter output level bit error rate fast eye mask eye contour display 8 color lcd t ouchscreen data entry touch-screen display, numeric ke ypad with up/down arrows, dial-knob control or usb keyboard and mouse. hard disk for local storage of user patterns and data. internal or external disk a vailable. removable storage floppy d isk driv e 1.44 mb usb stick online help for comprehensive sof tware support interfaces gpib (ieee 488), l an, parallel printer port, vga output, 4 x usb 2.0, 1 x usb 1.1 ports page 2/10 serialbert 7 gbps
user interface the time needed to set up the f irst measure- ment is minimised based on intuitive and easy- to-learn inter faces. the N4902B serialbert 7 gbps user inter face is easily fitted to a variety of applications. in addition, the optimized measurement suite guar- antees an immediate return on investment. the user interface provides the f ollo wing functions: patter generator setup error setup anal yser / detector pattern editor measurement results by utilizing netw ork capabilities, N4902B serialbert is remote controllable via lan. gpib is available for ms windo ws, u nix or linux operating syst ems. test ex ecutives can control the system by using n ational instr uments labview, agilent t estex ec, and microsoft? excel or vi sual basic. examples for results screens the generator pattern editor allows simple access to timing & level paramet ers, as seen below. figure 1: generator setup figure 3: pattern editor setup figure 2: error detector setup figure 4: g.821 results serialbert 7 gbps page 3/10 the diagram below shows bit error results based on ccitt ref. g.821. the sampling point setup allows sim ple access to sampling p oint precision refer ring to timing point t hreshold. the patter n editor allows the operator to deal with user-specific data.
figure 5: spectral jitter figure 6: bert scan incl. rj/dj separation figure 7: output level & q factor measurement suite the measurement suite of the serialbert 7 gbps offers com prehensive analysis f eatures, detailed insight for design v erif ication and effi- cient pass/fail t esting in manufacturing. spectral jitter decomposition (see fig. 5) it includes a measurement f or the spectral decom position of jitter components. the decom- position t echnique allows inband- and outband- charact erization of cir cuits and de vices includ- ing plls and cdrs. while debugging designs, the new measurement allows the exploration of the various components of deter ministic jitter. bert scan incl. rj / dj separation (see fig. 6) this measurement shows the ber of the duts output versus sample point delay, which is dis- played as a curve with ber vs. sam ple delay and t hreshold. available results are setup/hold time, phase margin, jitter incl. extrapolation of total jitter (rms, peak- to-peak) and rj/dj separation. the output timing measurement is available as a bat htub plot and as a histogram. this provides measurement of rj, dj and total jitter. the measurement method is equivalent to the iee802.3ae met hod. in order to guarantee the validity of the measurement, a "quality of fit" value is also pro vided. output level and q factor (see fig. 7) figure 7 shows the sample bert delay corre- sponding to the threshold. available results are q factor, t able. eye contour (see fig. 8) for device characterization the eye opening measurement generates a three-dimensional bit error rate (ber) diag ram as a function of the sample delay and the sam ple t hreshold. besides the eye opening, the eye cont our measurement provides results for the optimum sample point. the eye opening measurement allo ws selecting different views such as eye contour, pseudo color and equal ber plots. fast eye mask for fast pass/fail t esting in manufacturing, this measurement checks up to 32 points, equivalent to mask t esting. figure 8: eye contour page 4/10 serialbert 7 gbps
features: polarity - normal or inverted data data high level adjust data amplitude adjust clock/data relative delay adjustment vertical data-eye cr oss-over adjust output gating error add delay control input pattern generator waveform examples for differential data output pulse perfor mance measurement allows diff erent amplitude voltages with variable am plitudes from 50mv 1.8v, output volt age. the window makes -2v2.8v possible and a variable delay. an exam ple is shown below in figure 10. figure 9: front view of pattern generator figure 10: 50% signals at 2v table 1: parameters for serialbert 7 gbps general range of operation: 620 mbps to 7 gbps interface differential or single-ended (1) , dc coupled, 50 ? format nrz, normal or inverted amplitude/resolution 0.10 v to 1.8 v in 5 mv steps output voltage window -2.0 v to +3.0 v predefined levels ecl, pecl (3.3v), lvds, cml transition times < 25 ps pp (2) (10% to 90%) jitter 9 ps pp typical clock/data delay 0.75 ns resolution 100 fs terminations 50 ? , -2 v to 3 v or 50 ? ac coupled (the external termination voltage must be below the output high level) crossing point of adjustment 20%.......80% typical single error inject adds single errors on demand fixed error inject fixed error ratios of 1 error in 10 n bits, n = 3, 4, 5, 6, 7, 8, 9 delay control input 100ps, dc to 1 ghz @ data rate <10.5 gpbs connector 2.4 mm female (1) in single-ended mode the unused output has to be terminated by a 50 ? ? resistor to ground (2) at ecl levels serialbert 7 gbps page 5/10 table 2: parameters for N4902B serialbert 7 gbps generator clock output 1, differential or single-ended, 2.4mm(f) (1) frequency 620 mhz - 7 ghz impedance 50 ohm typ. amplitude/resolution 0.1vpp to 1.8 vpp in 5mv steps output voltage window -2.00 to +2.80 v short circuit current 72 ma max. external termination voltage -2v to +3v (2) addressable technologies lvds, cml pecl; ecl (terminated to 1.3v/0 v/-2 v) low voltage cmos transition times (10%-90%) <25 ps jitter 1 ps rms typ. ssb phase noise < - 75 dbc with internal clock source (10ghz@ 10khz offset, 1hz bandwidth) (1) in single-ended mode, the unused output must be terminated with 50 ohm to gnd. (2) external termination voltage must be less than 3v below v oh . external termination voltage must be less than 3v above v ol . termination into ac is possible. clock output 10 mhz reference input a 10 mhz ref erence signal can be applied from which the internal clock is derived. table 3: specifications interface ac coupled, 50 ? nominal amplitude 200 mv to 2 v connector sma female data output
table 5: delay control input interface dc coupled, 50 ? nominal input voltage window -250 mv to +250 mv delay range -100 ps to + 100 ps modulation bandwidth dc to 1 ghz connector sma female trigger output this pro vides an electrical trigger synchronous with the pattern for use with an oscilloscope or other test equipment. there is a fixed delay of 32 ns typical between trigger and data output for the selected bit. it operates in two modes: pattern trigger and divided clock trigger. pattern trigger mode for prbs patterns the pulse is synchr onized with a user specif ied trigger pattern. the repe- tition rate is 1 pulse for every 4th pattern rep- etition. for alternate patterns the trigger pulse occurs at bit 0 of the selected pattern. for all other patterns, the trigger pulse is synchr onized to a user-def inable bit in the pattern. divided clock mode in divided clock mode the trigger is a square wave at the clock rate divided by 2, 4, 8, 10, 16, 20, 40, 64, 128. table 6: specifications pulse width square wave levels high: +0.5 v; low -0.5 v typ. transition times 35 ps typical interface dc coupled, 50 ? nominal connector sma female figure 12: sinusoidal jitter figure 13: random jitter auxiliary input this port can be used to control user programmable, alternate t est patterns or inhibit data output (force the output data to a fixed low level). when alternate pattern mode is selected the instr ument will output one of two patterns (a or b). the auxiliary in put controls which pattern is output in one of two modes. in both modes, swit ching between patterns is at the end of a pattern and is hitless (error free). page 6/10 serialbert 7 gbps table 4: clock input frequency range 620 mhz to 7 ghz interface ac coupled, 50 ? nominal amplitude 150 mv to 2 v connector sma female clock input clock scheme figure 11: block diagram for the clock section t hree clock paths are possible: 10 mhz ref. input used to synchronise serialbert 7 gbps with other equipment at 10 mhz ext. clock in put operates from 620 mhz to 7 ghz. this allows the in put of a fm modulated clock for jitter t ransfer or jitter t olerance measurements internal clock ref erence operates from 620 mhz to 7 ghz modulation face modulation operates betw een 620 and 7 gbps. it is a linear ? d /? t function t hat allows diverse signal distor tions to be added.
table 7: specifications interface dc coupled, 50 ? ? nominal levels ttl levels minimum pulse width 100 ns connector sma female table 8: specifications interface dc coupled, 50 ? nominal levels ttl compatible minimum pulse width 100 ns connector sma female figure 14: external trigger pulse patterns prbs (hw generated) 2 31 - 1 polynomial: x 31 + x 28 + 1 = 0 (inverted) 2 23 - 1 polynomial: x 23 + x 18 + 1 = 0 (invert ed) (itu-t o.151) 2 15 - 1 polynomial: x 15 + x 14 + 1 = 0 (invert ed) (itu-t o.151) 2 11 - 1 polynomial: x 11 + x 9 + 1 = 0 (invert ed) (itu-t o.152) 2 10 - 1 polynomial: x 10 + x 7 + 1 = 0 (inverted) 2 7 - 1 polynomial: x 7 + x 6 + 1 = 0 (invert ed) (itu-t v .29) zero substitution zeros can be substituted for data to ext end the longest run of zeros in t he patterns below. the longest run can be extended to the pattern length -1. the bit f ollo wing the substituted zeros is set to 1. variable mark density the ratio of ones to to tal bits in the patterns below can be set to 1/8, 1/4, 1/2, 3/4, or 7/8. available test patterns for zero and variables: 8388608 bits based on 2 23 -1 prbs 32768 bits based on 2 15 -1 prbs 8192 bits based on 2 13 -1 prbs 2048 bits based on 2 11 -1 prbs 1024 bits based on 2 10 -1 prbs 128 bits based on 2 7 -1 prbs user-programmable test patterns user defined patterns are a vailable with variable length from 1 bit to 33,554,432 bits (2 25 ). alternate test pattern switch between two equal length user programmable patter ns, each up to 16,777,216 bits. switching is po ssible by using a front panel key, gp -ib or the auxiliary in put port. changeover is synchr onous with the end of the pattern. the length of the alter nating patterns should be a multiple of 512 bits. two met hods of contr olling pattern changeover are a vailable: one-shot and alternate. external error inject input the external error inject input adds a single error to the dat a output for each rising edge at the input. serialbert 7 gbps page 7/10 mode 1: one-shot a rising edge on the auxiliary input inserts a single v ersion of pattern b into repetitions of pattern a. mode 2: alternate the logic state of the signal at the auxiliary input determines which pattern is output. an active (ttl high) signal will output pattern 3. the auxiliary in put may also be used to in hibit the data output signal. if alternate pattern mode is not selected, an active (ttl high) signal at the auxiliary in put port forces (gates) the data to a logic zero at the next 32-bit boundary in the pattern. auxiliary input switch between two diff erent data sequences using an external trigger pulse table 9: delay control input interface dc coupled, 50 ? nominal input voltage window -250 mv to +250 mv delay range - 100 ps to +100 ps @ 7 gbps modulation bandwidth dc to 1 ghz connector sma female delay control input the delay control modulates the delay of the data ouputs.
errors output this provides an ele ctrical signal to indicate received err ors. the output is the l ogical 'or' of errors in a 128-bit segment of the data. table 13: specifications interface format rz, active high interface dc coupled, 50 ? nominal levels high: 1v nominal; low: 0 v nominal pulse width 128 clock periods connector sma female table 10: parameters for N4902B error detector range of operation 620 mbps to 7 gbps impedance single-ended: 50 ? , -2.0v to +3.0v terminated (1) differential: 100 ? termination voltage -2 v to +3 v or off (true differential mode) (1) format nrz max input amplitude 2.0 v sensitivity <50 mv pp (2) decision threshold range -2 v to +3 v in 0.1 mv steps max levels -2.2v to +3.2v phase margin 1ui - 12ps typical (3) clock/data phase alignment 0.75 ns in 100 fs steps clock data recovery (cdr) 4.23 gbps to 6.40 gbps 2.11 gbps to 3.20 gbps cdr output jitter 0.01 ui rms typical connector 2.4 mm female (1) a user has to define a 2v operating voltage window, which is in the range between -2.0 v to +3.0 v. data signals, termina- tion voltage and decision threshold have to be within this volt- age window. (2) @ 10 gbps, ber 10 -12 , prbs 2 31 -1. (3) based on internal clock gating input the gating in put is used to enable the error count ers including during burst gating mode. in both these cases the err or counters will always be enabled for a multiple of 512 pattern bits table 14: gating input interface levels ttl levels pulse width 256 clock periods connector sma female connecting an exter nal ter mination to the gating in put will pull it low and disable the instr ument error counters. gating resumes when the gating input returns high. aux output this output can be used to pro vide either clock or data signals: clock: clock signals from the in put or recov- ered clock signals in cdr mode. data: data after being com pared with the t hreshold. page 8/10 serialbert 7 gbps error detector data input features: differential data in puts data polarity - normal or inverted data. clock/data delay adjust. clock/data aut o-alignment. 0/1 decision t hreshold auto-alignment. clock data recovery (cdr) for selected frequency ranges or ext. clock table 12: specifications interface dc coupled, 50 ? nominal levels high: + 0.5 v; low: - 0.5 v minimum pulse width pattern length x clock period/2 at 10gb/s with 1000 bits = 50 ns connector sma female figure 15: front view error detector clock input table 11: specifications frequency range 620 mhz to 7 ghz interface ac coupled, 50 ? nominal amplitude 100 mv to 1.2 v connector sma female trigger out error detector pattern trigger output this provides an electr onic trigger synchronous with the selected error detector reference pat- tern. it operates in two modes, pattern trigger and divided clock trigger. pattern trigger mode this pro vides an electrical trigger synchronous with the selected error detector reference pattern. in pattern mode the pulse is synchronized to repetitions of the output pattern. for prbs patterns the repetition rate is 1 pulse for every 4th pattern repetition divided clock mode in divided clock mode the trigger is a square wave at the clock rate divided by 4, 8, 16, 32, 40, 64, 128. possibilites for cdr mov ement or external clock in put.
automatic clock-to .data alignment an important feature of the serialbert error detector is the ability to aut omatically align the clock and data inputs such t hat the error detector samples are in the middle of the eye (in the time axis). audible error indicator selectable to indicate errors, instant aneous error ratios, and errors above user -def ined thresholds. on/off volume contr ol, and audible pitch changes with higher pitch cor responding to higher ber automatic 0/1 threshold centre the 0/1 t hreshold center operation is used to set the 0/1 t hreshold midway between two points, top and bottom of the eye where the bit error ration is equal to a selectable t hreshold. there are t hree met hods of determining the 0/1 threshold of in put signals at the error detector data input: manual, automatic track and automatic center. manual 0/1 t hreshold can be set manually. automatic track this continuously tracks the mean dc level of the input signal and adjusts the threshold accordingly. the 0/1 t hreshold calculated is display ed. adjustment is made within appro ximately 100ms. limited to a 2v window selected by the user. automatic centre the error detector sets the 0/1 t hreshold mid- way between two points, the top and bottom of the eye, where the bit error ratio is equal to a selectable t hreshold. table 15: specifications of aux out interface ac coupled, 50 ? nominal amplitude 600 mv nominal connector sma female the eye height is calculated and displayed. it is limited to a 2v window selected by the user. cable droop compensation the N4902B serialbert 7 gbps provides an excellent waveform at the end of a 24 cable (n4910a). the cable dr oop is com pensated and there is an excellent t ransition time <25 ps. mechanical parameters upgrade 7 gbps - 13.5 gbps agilent offers a factory-b ased upg rade possibili- ty for the N4902B serialbert from 7 gbps to 13.5 gbps. for t his service, please contact agilent technologies. the upgrade requires the follo wing or der instr uctions: order instructions N4902B serialbert 7 gbps, usb mouse io-configuration: N4902B-100 pattern generator & erro r detector N4902B-200 pattern generator only N4902B-300 error detector only calibration/test data: N4902B-uk6 commercial calibration with test data accessories: n4910a cable kit: 2.4mm matched cable pair n4911a-002 adapter 3.5mm female to 2.4 mm male n4912a 2.4mm, 50 ohm termination, male warranty r1280a standard warranty: 3 years return-to- agilent extended warranty: 5 years return-to-agilent calibration r1282a calibration plans are available to order for 3 or 5 years; calibration interval 12 month figure 16: automatic optimum sampling point location table 16: general mainframe characteristics operating temperature 5 c to 40 c storage temperature -40 c to +70 c humidity 5 - 40 c, 95% rel.humidity power requirements 100 - 240 vac, 10%, 47 - 63 hz, 350 vac physical dimensions width: 424.5 mm height: 221.5 mm depth: 580.0 mm weight (net) 24.5 kg weight (shipping) (max) 36.0 kg serialbert 7 gbps page 9/10 table 17: upgrades 7 gbps - 13.5 gbps order no. feature n4900as-101 upgrade version n4902a-100 to 13.5gb/s n4900as-102 upgrade version n4902a-200 to 13.5gb/s n4900as-103 upgrade version n4902a-300 to 13.5gb/s
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